Bao Liu

Dr. Liu has over 25 years of experience in EDA industry and academia. He worked with China IC Design Center, Conexant Systems, Incentia Design Systems, Cadence Design Systems, BlazeDFM, Tabula, and Mentor Graphics on layout compaction, EM verification, delay calculation, timing fix, timing analysis, and placement, respectively. He also worked as an assistant professor at the University of Texas at San Antonio from 2008 to 2015 on statistical timing analysis, signal integrity analysis, path delay test, error-resilient and better-than-worst-case design, nano-architecture and hardware and system security. Dr. Liu received his B.S. and M.S. degrees in Electrical Engineering at Fudan University in 1993 and 1996, and Ph.D. degree in Computer Science at University of California San Diego in 2003, respectively. He received an honor medal in China Mathematics Olympiad in 1988. Dr. Liu has over 70 academic publications in scientific journals and conference proceedings. He holds three PCT/US patents.  

Academic Publications

Journal Articles

Hardware Security

  • B. Liu and R. Sandhu, " Fingerprint-Based Detection and Diagnosis of Malicious Programs in Hardware ," IEEE Trans. on Reliability Special Section on Trustworthy Computing, 64(3), 2015, pp. 1068-1077 .
  • B. Liu and B. Wang, " Reconfiguration-Based VLSI Design for Security ," IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS) , 5(1), 2015, pp. 98-108.

    VLSI Testing

  • B. Liu and L. Wang, " Dynamic Statistical Timing Analysis-Based VLSI Path Delay Test Pattern Generation ," IEEE Trans. on VLSI Systems , 23(9), 2014, pp. 1577-1590.

    Resilient Design

  • V. De, A. B. Kahng, T. Karnik, B. Liu, M. Maleki and L. Wang, " Application-Specific Cross-Layer Optimization Based on Predictive Variable-Latency VLSI Design ,"  ACM Journal on Emerging Technology in Computing Systems , 12(3), 2015, Article No. 21, pp. 21:1-21:19.
  • B. Liu, L. Wang and F. Teshome, "Error-Detecting Code-Based Minimum Logic of Guaranteed Timing/Soft Error Resilience," Journal of Computer Science and Engineering , 17(1), 2013, pp. 1-10.
  • B. Liu, X. Chen and F. Teshome, " Resilient and Adaptive Performance Logic ," ACM Journal on Emerging Technology in Computing Systems , 8(3), Article No. 22, 2012, pp. 1-16.

    Nano-Architecture

  • B. Liu, " Voltage-Controlled Nano-Addressing for Nano-System Communication ," Nano Communication Networks Journal , 1(3), 2010, pp. 224-231.
  • B. Liu, " Architecture Exploration of Crossbar-Based Nanoscale Reconfigurable Computing Platforms ," Nano Communication Networks Journal , 1(3), 2010, pp. 232-241 (Ranked No. 3 in ScienceDirect Top 25 Hottest Articles).

    Signal Integrity and Statisitical Timing Analysis

  • B. Liu and S. X.-D. Tan, " Minimum Decoupling Capacitor Insertion in VLSI Power/Ground Supply Networks by Semidefinite and Linear Programs ," IEEE Trans. on VLSI Systems , 11(8), 2007, pp. 1284-1287.
  • A. B. Kahng, B. Liu, and Q. Wang, " Stochastic Power/Ground Supply Voltage Prediction and Optimization via Analytical Placement ," IEEE Trans. on VLSI Systems , 15(8), 2007, pp. 904-912.
  • A. B. Kahng, B. Liu, and X. Xu,  " Statistical Timing Analysis in the Presence of Signal Integrity Effects ," IEEE Trans. on Computer-Aided Design of VLSI Systems , 2007.

    Physical Design

  • A. B. Kahng, B. Liu, and I. Mandoiu, " Non-Tree Routing for Reliability and Yield Improvement ," IEEE Trans. on Computer-Aided Design , 23(1), 2004, pp. 148-156.  
  • C. Albrecht, A. B. Kahng, B. Liu, I. Mandoiu, and A. Zelikovsky, " On the Skew-Bounded Minimum-Buffer Routing Tree Problem ," IEEE Trans. on Computer-Aided Design , 22(7), 2003, pp. 937-945.
  • C. Alpert, A. B. Kahng, B. Liu, I. Mandoiu and A. Zelikovsky,  " Minimum Buffered Routing with Bounded Capacitive Load for Slew Rate and Reliability Control ," IEEE Trans. on Computer-Aided Design , 22(3), 2003, pp. 241-253.
  • C. J. Alpert, G. Gandham, M. Hrkic, J. Hu, A. B. Kahng, J. Lillis, B. Liu, S. T. Quay, S. S. Sapatnekar and A. J. Sullivan, " Buffered Steiner Trees for Difficult Instances ," IEEE Trans. on Computer-Aided Design , 21(1), 2001, pp. 3-14.
  • C.-K. Cheng, A. B. Kahng, B. Liu and D. Stroobandt, " Toward Better Wireload Models in the Presence of Obstacles ," IEEE Trans. on VLSI Systems , 10(2), 2002, pp. 177-188.
  • B. Liu and P. S. Tang, "Firmware System Realization of VLSI Design Rule Check," Chinese Journal of Electronics , 24(11), 1996.

    • Conference Papers

    Hardware Security

  • B. Liu and B. Wang, " Embedded Reconfigurable Logic for ASIC Design Obfuscation Against Supply Chain Attacks ," Design Automation and Test in Europe (DATE) , 2014.

    VLSI Testing

  • B. Liu, " Input-Aware Statistical Timing Analysis for VLSI Delay Test and Average Design (invited) ," International Midwest Symposium on Circuits and Systems (MWSCAS) , 2014.
  • B. Liu and C.-H. Chen, " Testing, Diagnosis and Repair Methods for NBTI-Induced SRAM Faults ," International Conference on IC Design and Technology (ICICDT) , 2014.
  • L. Wang, X. Wang, M. Maleki and B. Liu, " Power/Ground Supply Voltage Variation-Aware Delay Test Pattern Generation ," IEEE VLSI Test Symposium (VTS) , 2014.
  • B. Liu and L. Wang, " Input-Aware Statistical Timing Analysis-Based Delay Test Pattern Generation ," International Symposium on Quality Electronic Design (ISQED) , pp. 454-459, 2013.

    Resilient Design

  • B. Liu, L. Wang and J. Portillo, " Variable Latency VLSI Design Based on Timing Analysis, Delay ATPG, and Completion Prediction ,"  Midwest Symposium on Circuits and Systems (MWSCAS) , 2013, pp. 653-656.
  • B. Liu and L. Wang, " Minimum Logic of Guaranteed Single Soft Error Resilience Based on Group Distance-Two Code ," International Conference on IC Design and Technology (ICICDT) , 2012, pp. 193-196.
  • B. Liu, X. Chen and F. Teshome, " Delay Insensitive Code-Based Timing and Soft Error-Resilient and Adaptive-Performance Logic ,"International Symposium on Quality Electronic Design (ISQED) , 2012, pp. 63-72.
  • B. Liu, " Error-Detecting/Correcting-Code-Based Robust Nanoelectronic Circuits ," NASA/ESA Conference on Adaptive Hardware and Systems (AHS) , 2010, pp. 66-72.
  • B. Liu, " Robust Differential Asynchronous Nanoelectronic Circuits ," International Symposium on Quality Electronic Design , 2009, pp. 97-102.

    Nano-Architecture

  • B. Liu, "  Advanced in Crossbar-Based Nanoscale Reconfigurable Computing Fabrics (invited) ," IEEE/ACM International Midwest Symposium on Circuits and Systems(MWSCAS) , 2010, pp. 17-20.
  • B. Liu, Z. Cao, J. Tao, X. Zeng, P. Tang and H.-S. P. Wong, " Intel LVS Logic as a Combinational Logic Paradigm in CNT Technology ," IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) , 2010, pp. 77-81.
  • B. Liu, " A Linear Complexity Incremental Defect mapping Method for Reconfigurable Computing Platforms in the Presence of Prevalent Defects ," Austin Conference on Integrated Systems and Circuits (ACISC) , 2009.
  • B. Liu, "  Defect Mapping and Adaptive Configuration of Nanoelectronic Circuits Based on a CNT Crossbar Nano-Architecture ," Workshop on Nano, Molecular, and Quantum Communications (NanoCom) , 2009, pp. 1-6.
  • B. Liu, " Adaptive Voltage Controlled Nanoelectronic Addressing for Yield, Accuracy and Resolution ," International Symposium on Quality Electronic Design , 2009, pp. 430-435.
  • B. Liu, " Reconfigurable Double Gate Carbon Nanotube Field Effect Transistor Based Nanoelectronic Architecture ," Asia and South Pacific Design Automation Conference , 2009, pp. 853-858.
  • B. Liu, " A Voltage Controlled Carbon Nanotube Addressing Circuit ," International Conference on Nano-Networks , 2008, pp. 66-68.
  • B. Liu, " Performance Variation Adaptive Differential Signaling via Carbon Nanotube Bundles ," Internationl Conference on Solid-State and Integrated-Circuit Technology , 2008, pp. 559-562.

    Signal Integrity and Statisitical Timing Analysis

  • Y. Chen, A. B. Kahng, B. Liu and W. Wang, "Crosstalk-Aware Signal Probability-Based Dynamic Statistical Timing Analysis," International Symposium on Quality Electronic Design (ISQED) , 2015.
  • Z. Hao, R. Shen, S. X.-D. Tan, B. Liu, G. Shi and Y. Cai, "Statistical Full-Chip Dynamic Power Estimation Considering Spatial Correlations," International Symposium on Quality Electronic Design (ISQED) , 2011.
  • B. Liu, " Lagrangian Relaxation Based Congestion Driven Analytical Placement (invited) ," International Conference on Computational Problem-Solving (ICCP) , 2010.
  • K. Mohammad, B. Liu, and S. Agaian, "Energy Efficient Swing Signal Generation Circuits for Clock Distribution Networks," IEEE International Conference on Systems, Man, and Cybernetics , 2009, pp. 3495-3498.
  • B. Liu, " On VLSI Statistical Timing Analysis and Optimization (invited) ," IEEE International Conference on ASIC (ASICON) , 2009.
  • B. Liu, " Analysis and Extraction of Parametric Variation Effects on Microfluidics-Based Biochips ," IEEE International Behavioral Modeling and Simulation Conference (BMAS) , 2009, pp. 60-65.
  • B. Liu, "  Analog/RF Design Techniques for High Performance Nanoelectronic On-Chip Interconnects ," Internationl Conference on Solid-State and Integrated-Circuit Technology , 2008, pp. 1831-1834.
  • B. Liu, " Signal Probability Based Statistical Timing Analysis ," Design Automation and Test in Europe , 2008, pp. 562-567.
  • B. Liu, " Spatial Correlation Extraction via Product Chip Performance Statistics ," Design Automation and Test in Europe , 2008, pp. 527-532.
  • A. B. Kahng, S. M. Kang, W. Li and B. Liu, " Efficient Analytical Thermal Placement for VLSI Lifetime Reliability Improvement and Minimum Performance Variation ," International Symposium on Quality Electronic Design , 2007, pp. 71-77.
  • X. Yuan, J. Fan, B. Liu and S. X.-D. Tan, "Stochastic Extended Krylov Subspace Based Method for Power/Ground Network Analysis," International Conference on ASIC , 2007.
  • B. Liu, " Statistical Gate Level Simulation based on Parameterized Current Models for Process and Signal Variations ," International Symposium on Quality Electronic Design , 2007, pp. 257-261.
  • B. Liu, A. B. Kahng, X. Xu, J. Hu and G. Venkataraman, " A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield ," Asian and South Pacific Design Automation Conference , 2007, pp. 24-31.
  • B. Liu and A. B. Kahng, " Expected Performance Centering for Analog/RF Designs ," Behavior Modeling and Simulation Conference , 2006, pp. 23-27.
  • B. Liu and A. B. Kahng, " Statistical Gate Level Simulation via Voltage Controlled Current Source Models ," Behavior Modeling and Simulation Conference , 2006, pp. 23-27.
  • B. Liu, " Stochastic Power Supply Voltage Drop Prediction via Efficient Statistical Supply Current Analysis ," Electronic Design Processes Workshop , 2006.
  • A. B. Kahng, B. Liu, and X. Xu, " Statistical Gate Delay Calculation with Crosstalk Alignment Consideration ," Great Lakes Symposium on VLSI , 2006, pp. 223-228.
  • A. B. Kahng, B. Liu, and X. Xu, " Statistical Crosstalk Aggressor Alignment Aware Interconnect Delay Calculation ," System Level Interconnect Prediction , 2006, pp. 91-97.
  • A. B. Kahng, B. Liu, and S. Tan, " Efficient Decoupling Capacitor Planning via Convex Programming Methods ," Internationl Symposium on Physical Design , 2006, pp. 102-107.
  • A. B. Kahng, B. Liu, and S. Tan, " SMM: Scalable Analysis of Power Delivery Networks by Stochastic Moment Matching ," International Symposium on Quality Electronic Design , 2006, pp. 638-643.
  • A. B. Kahng, B. Liu, and X. Xu, " Constructing Current-Based Gate Models Based on Existing Timing Library ," International Symposium on Quality Electronic Design , 2006, pp. 37-42.

    Physical Design

  • A. B. Kahng, B. Liu and Q. Wang, "  Supply Voltage Degradation Aware Placement ," International Conference on Computer Design , 2005, pp. 437-443. ( Best Paper Award )
  • A. B. Kahng and B. Liu, "  Q-Tree: A New Iterative Improvement Approach for Buffered Interconnect Optimization ," IEEE Computer Society Annual Symposium on VLSI , 2003, pp. 183-188.
  • A. B. Kahng, B. Liu, and I. Mandoiu, " Non-Tree Routing for Reliability and Yield Improvement ," Proc. IEEE/ACM Intl. Conference on Computer-Aided Design , 2002, pp. 260-266.
  • C. Albrecht, A. B. Kahng, B. Liu, I. Mandoiu and A. Zelikovsky, " On the Skew-Bounded Minimum Buffer Routing Tree Problem ," Tenth Workshop on Synthesis And System Integration of Mixed Technologies , 2001, pp. 250-256.
  • C. J. Alpert, A. B. Kahng, B. Liu, I. Mandoiu, J.-D. Nale and A. Zelikovsky, " Minimum-Buffered Routing for Slew Rate and Reliability Control ," Proc. International Conference on Computer-Aided Design , 2001, pp. 408-415.
  • C. J. Alpert, M. Hrkic, J. Hu, A. B. Kahng, J. Lillis, B. Liu, S. T. Quay, S. Sapatnekar, A. J. Sullivan, P. Villarrubia, " Buffered Steiner Trees for Difficult Instances ," Proc. ACM International Symposium on Physical Design , 2001, pp. 4-9.
  • C.-K. Cheng, A. B. Kahng and B. Liu, " Interconnect Implication of Growth-Based Structural Models for VLSI Circuits ," Proc. ACM International Workshop on System-Level Interconnect Prediction , 2001, pp. 99-106.
  • C.-K. Cheng, A. B. Kahng, B. Liu and D. Stroobandt, " Toward Better Wireload Models in the Presence of Obstacles ," Proc. Asia and South Pacific Design Automation Conference , 2001, pp. 527-532.

    • Technical Reports

    Signal Integrity and Statisitical Timing Analysis
  • B. Liu, X. Xu and A. B. Kahng, "  SSTA-SI: Signal Integrity Effects Aware Statistical Static Timing Analysis ," UCSD Technical Report CS2007-0883 .
  • B. Liu, " Maximum Instantaneous Power Estimation by Subgraph Coloring ," UCSD Technical Report CS2005-0834 .
  • B. Liu, " Charge Matching Based Tail Approximation in a Piecewise Linear-and-Exponential Function ," UCSD Technical Report CS2005-0835 .
  • B. Liu, "  NP-Completeness and Approximation Scheme of Zero-Skew Clock Tree Problem ," UCSD Technical Report CS2005-0837 .

    • Book Chapter and Dissertation

    Nano-Architecture

  • B. Liu, "  Towards Robust, High Performance and Low Power Nanoelectronic Design ," VLSI , ISBN 978-3--902613-50-9, 2009.

    Physical Design

  • B. Liu,  VLSI Interconnect Synthesis and Prediction , Dissertation, Department of Computer Science and Engineering, University of California San Diego, 2003.

    • Patent Publication

    Resilient Design

  • B. Liu, " Error-Detecting/Correcting-Code Enhaced Self-Checked/Corrected/Timed Nanoelectronic Circuits ," # WO 2011/109713 A2 , 9 September, 2011.

    FPGA Architecture

  • B. Liu, " Compact Regular Reconfigurable Fabrics ," # WO 2012/061501 A2 , 10 May, 2012.

    Nano-Architecture

  • B. Liu, "  Carbon Nanotube Crossbar Based Nano-Architecture ," # US 2013/0033310 A1 , Feb. 7, 2013.